Area-Delay-Power Efficient Carry-Select Adder

ABSTRACT                             In this paper, we made an analysis on the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA to study the data-dependency and to identify redundant logic operations. We have eliminated all the redundant logic operations present in conventional CSLA and proposed a new logic […]

Area-Delay Efficient Binary Adders In Qca

  ABSTRACT: As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design […]

Improved 8-Point Approximate Dct For Image And Video Compression Requiring Only 14 Additions

  ABSTRACT Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT Transforms have […]

High-Throughput Multi Standard Transform Core Supporting Mpeg/H.264/Vc-1 Using Common Sharing Distributed Arithmetic

ABSTRACT This paper proposes a low-cost high-throughput multi standard transform (MST) core, which can support MPEG- 1/2/4 (8 × 8), H.264 (8 × 8, 4 × 4), and VC-1 (8 × 8, 8 × 4, 4×8, 4×4) transforms. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number […]