A Learning Framework for Age Rank Estimation Based on Face Images With Scattering Transform

  This paper presents a cost-sensitive ordinal hyperplanes ranking algorithm for human age estimation based on face images. The proposed approach exploits relative-order information among the age labels for rank prediction. In our approach, the age rank is obtained by aggregating a series of binary classification results, where cost sensitivities among the labels are introduced [...]

Formal Interpretation of Assertion-Based Features on AMS Designs

The paper proposes the adoption of formal methods for modeling of analog functions. It explains how assertions can be overlaid onto the range of values of individual features in an analog function, and proceeds toward building a mathematical (hybrid automata) model to represent and analyze them. An LDO regulator and a battery charger are used [...]

The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications

  The dependence of bias temperature instability (BTI) and hot carrier injection (HCI)-induced frequency degradation on interconnect length has been examined for the first time. Experimental data from 65-nm test chips show that frequency degradation due to BTI decreases monotonically for longer wires because of the shorter effective stress time, while the HCI-induced component has [...]

Harmonic Estimation Using Symmetrical Interpolation FFT Based on Triangular Self-Convolution Window

Harmonic estimation is an important topic in power system signal processing. Windowed interpolation fast Fourier transformation (WIFFT) is an efficient algorithm for power system harmonic estimation, which can eliminate the errors caused by spectral leakage and picket fence effect. However, the fitting polynomial in the interpolation procedure contains both even and odd terms, and this [...]

Physical Layer and Medium Access Control Design in Energy Efficient Sensor Networks: An Overview

  It is now well expected that low-power sensor networks will soon be deployed for a wide variety of applications. These networks could potentially have millions of nodes spread in complex indoor/outdoor environments. One of the major deployment challenges under such diverse communication environments is providing reliable communication links to those low cost and/or battery-powered [...]

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC

By integrating multiple processing units (PUs) and memories on a single chip, multiprocessor system-on-chip (MPSoC) can provide higher performance per energy and lower cost per function to applications with growing complexity. On the other hand, shrinking feature sizes and reducing power supply voltages also make MPSoCs more susceptible to various reliability threats, such as power/ground [...]

Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories

With the trend of increasing transient error rate, it is becoming important to prevent transient errors and provide a correction mechanism for hardware circuits, especially for SRAM cache memories. Caches are the largest structures in current microprocessors and, hence, are most vulnerable to the transient errors. Tag bits in cache memories are also exposed to [...]

A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems

This paper presents a voltage monitoring IC with high-voltage multiplexer (HVMUX) and HV transceiver for battery interconnect module (BIM) used in battery management systems (BMSs). The voltage monitoring IC must be able to accommodate input voltage up to tens of volts, perhaps even hundreds of volts, which is difficult to be realized using a logic-based [...]

Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution

This paper presents a low-complexity algorithm and the corresponding hardware based on the coordinated polynomial solutions for solving line spectrum pairs (LSPs). To improve the computation of LSPs, the enhanced Tschirnhaus transform (ETT) is proposed to accelerate the coordinated polynomial solution. The proposed ETT can replace fractional multiplication with addition and shift operations, so unnecessary [...]

Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems

In this paper, we propose a hardware-efficient mixed generalized high-radix (GHR) reconfigurable fast Fourier transform (FFT) processor for long-term evolution applications. The GHR processor based on radix-25/16/9 uses a 2-D factorization scheme as the high-radix unit and a 1-D factorization method as the system data routing technology. The 2-D factorization scheme is implemented by an [...]