IEEE 2015 VLSI Project

Z-TCAM An SRAM-based Architecture for TCAM

Ternary Content Addressable Memories (TCAMs) perform high-speed lookup operation but when compared with static random access memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive. Thus we formed a new architecture called Z-TCAM, which emulates the TCAM functionality with SRAM. Z-TCAM […]

A Dynamically Reconfigurable Multi-ASIP Architecture for Multi standard and Multimode Turbo Decoding

The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting […]

Energy Consumption of VLSI Decoders

Thompson’s model of very large scale integration computation relates the energy of a computation to the product of the circuit area and the number of clock cycles needed to carry out the computation. It is shown that for any sequence of increasing block-length decoder circuits implemented according to this model, if the probability of block […]

A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static […]

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm²

  A 6-bit full-binary compact and low-power current-steering digital-to-analog converter (DAC) designed for 60-GHz Wireless Personal Area Network applications is presented. The closely located circuit components based on the stacked unit cell minimize the parasitic capacitance and enhance the high-frequency dynamic linearity. The proposed binary structure realizes a compact DAC by eliminating the need for […]

( 4+2 log n ) Delta-G Modulo-(2^ Parallel Prefix n-3) Adder via Double Representation of Residues in [0,2]

The most popular modulus in residue number systems (RNS), next to power-of-two modulus, are those of the form ( ). However, in RNS applications that require larger dynamic range, without increasing the parameter, modulus of the form ( ) are gaining popularity. Nevertheless, latencybalanced computational channels in RNS arithmetic systems are desirable. Ripple-carry modulo-( ) […]

High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols

In a modern System on Chip (SoC) design, hundreds of cores and Intellectual Properties (IPs) can be integrated into a single chip. To be suitable for high-performance interconnects, designers increasingly adopt advanced interconnect protocols which support novel mechanisms of parallel accessing including outstanding transactions and out-of-order completion of transactions. To implement those novel mechanisms, a […]

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation. This CSA is also used […]

A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits

Advanced computing systems embed spintronic devices to improve the leakage performance of conventional CMOS systems. High speed, low power, and infinite endurance are important properties of magnetic tunnel junction (MTJ), a spintronic device, which assures its use in memories and logic circuits. This paper presents a PentaMTJ-based logic gate, which provides easy cascading, self-referencing, less […]

Ultralow-Energy Variation-Aware Design: Adder Architecture Study

Power consumption of digital systems is an important issue in nanoscale technologies and growth of process variation makes the problem more challenging. In this brief, we have analyzed the latency, energy consumption, and effects of process variation on different structures with respect to the design structure and logic depth to propose architectures with higher throughput, […]