Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm

Continuous technology scaling has made aging mechanisms, such as negative bias temperature instability and electromigration primary concerns in network-on-chip (NoC) designs. In this paper, we extensively analyze the effects of these aging mechanisms on NoC routers and links. We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads [...]

Signature Driven Hierarchical Post-Manufacture Tuning of RF Systems for Performance and Power

Signature Driven Hierarchical Post-Manufacture Tuning of RF Systems for Performance and Power

Integration of RF circuits in deeply scaled CMOS technologies and severe process variation in those technology nodes result in poor manufacturing yield. A post-manufacture tuning approach for yield improvement of RF systems is developed in this paper that uses hierarchical behavioral models of the RF systems. The proposed method first determines module-level performances from the [...]

A Low-Power Single-Phase Clock Multiband Flexible Divider

ABSTRACT From this research  a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a FPGA Spartan 3 XC 3s 400 PQ208. The multiband divider consists of a proposed wideband multi modulus 32/33/47/48 prescaler and 64/65/79/80 [...]

A Novel Modulo Adder for 2N-2K-1 Residue Number System

ABSTRACT: In the last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low complexity [...]

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

ABSTRACT Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. In this work, we focus on optimizing the design of the fused Add-Multiply (FAM) Operator for increasing performance. We investigate techniques to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form. We introduce a structured [...]

Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

ABSTRACT             This paper presents efficient distributed arithmetic (DA)-based approaches for high-throughput reconfigurable implementation of finite impulse response (FIR) filters whose filter coefficients change during runtime. Conventionally, for reconfigurable DA-based implementation of FIR filter, the lookup tables (LUTs) are required to be implemented in RAM; and the RAM-based LUT is found to be costly for [...]

Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits

ABSTRACT Design automation techniques are a key challenge in the widespread application of timing-robust asynchronous circuit styles. A new methodology for mapping multi rail logic expressions to NULL convention logic (NCL) gate library is proposed. The new methodology is then compared to another recently proposed mapping approach, demonstrating that the new methodology can further reduce [...]

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

ABSTRACT A multiplier-less architecture based on algebraic integer representation for computing the Daubechies 6-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using brute-force numerical optimization of the algebraic integer representation. The [...]

Eliminating Synchronization Latency Using Sequenced Latching

ABSTRACT Modern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. We propose a speculative method that hides synchronization latency by overlapping it with computation cycles. We verify [...]

Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm

ABSTRACT This paper presents a precise analysis of the critical path of the least-mean-square (LMS) adaptive filter for deriving its architectures for high-speed and low-complexity implementation. It is shown that the direct-form LMS adaptive filter has nearly the same critical path as its transpose-form counterpart, but   provides much faster convergence and lower register complexity. From [...]