Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

ABSTRACT

This brief presents a novel pipelined architecture for low-power, high throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the area complexity and reduce power consumption. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design.

EXISTING SYSTEM:

                     For discrete finite impulse response (FIR) Filters, the output y (n) is a linear convolution of weights w (n), and inputs. For an N-order FIR Filters, the generation of each output sample y (n) takes N + 1 multiply-accumulate (MAC) operations. Since general purpose multipliers require significant chip area, alternate methods of implementing multiplication are often used particularly when the coefficient values are known prior to implementation. A DA-based FIR adaptive filter implementation scheme is presented, which uses extra “auxiliary” LUTs to help in the updating; however, memory usage is doubled.

EXISTING SYSTEM TECHNIQUE:

  • Multiply and accumulate (MAC) units

EXISTING SYSTEM DRAWBACKS:

  • Low-Throughput
  • Occupied area high
  • Increase the system complexity

PROPOSED SYSTEM:

The computation of adaptive filters of large orders needs to be decomposed into small adaptive filtering blocks since DA based implementation of inner product of long vectors requires a very large LUT.

PROPOSED SYSTEM BLOCK DIAGRAM:

Proposed structure of DA-based LMS adaptive filter of length N = 16 and P = 4:

PROPOSED SYSTEM ALGORITHM:

  • LMS Adaptive Algorithms

PROPOSED SYSTEM ADVANTAGES:  

  • Low-Area
  • High-Throughput
  • Low-Power

SOFTWARE REQUIREMENT:

  • ModelSim6.4c
  • Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

  • FPGA Spartan 3/ Spartan 3AN

REAL TIME APPLICATION:

  • Digital communication & Signal processing applications
  • Digital radio receivers
  • Down converts
  • Software Radio

FUTURE ENHANCEMENT:

We will modify the proposed system by reducing the Area of Structure of the four-point inner-product block.

ALTERNATE TITLES:

Title 1: Adaptive Fir Filter Based On Distributed Arithmetic

Title 2: Distributed Arithmetic Adaptive Fir Filter Implementation Based On FPGA

Title 3: Adaptive Fir Filter Implementation Using Verilog HDL

PROJECT FLOW:

First Phase:

60% of Base Paper (3 Modules only Simulation)

Second Phase:

Remaining 40% of Base Paper with the Future Enhancement (Modification)