Mar 16 2015
Quaternary Logic Lookup Table in Standard CMOS
Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltagemode structures. A clock boosting technique is used to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS technology, able to work at 100 MHz while consuming 122 μW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.
INSPEC: CONTROLLED INDEXING
INSPEC: NON CONTROLLED INDEXING
- binary LUT structure
- clock boosting technique
- delays
- energy consumption
- field programmable gate arrays
- frequency 100 MHz
- full adder prototype
- interconnection impact reduction
- level transitions
- logic lookup table
- multiple valued logic
- power 122 muW
- power consumption optimization
- power efficiency
- power-hungry current-mode cells
- quaternary operation
- simple voltage-mode structures
- single voltage supply
- size 130 nm
- standard CMOS digital circuit process
- switches resistance optimization